Smart Metering: Security threats and Counter measures→

/ International Malware Conference/

Energy theft and meter tampering are world-wide problems that contribute heavily to revenue losses. Consumers have been found manipulating their electric meters, causing them to stop, under-register or even bypass the meter, effectively using power without paying for it. Apart from preventing physical tampers requiring smart solutions on chip, smart grid technologies are now in the process of being deployed. These solutions require a combination of different technologies and rely on network connectivity, posing significant security issues that must be addressed from the beginning. This paper covers vulnerabilities, challenges and techniques to prevent tampering in an energy meter, improving overall security (hardware and software) in a smart grid.

 

Kinetis ARM Cortex-M4 Microcontrollers -The most scalable portfolio of low power, mixed-signal MCUs

/ ARM Technology Symposium/

Technical Session on Freescale most scalable MCU: Kinetis based on ARM Cortex M4 core. Presentation covers Key Positioning, Key differentiators, Kinetis overview along with Tools and Enablement offering from Freesale.

.entry-summary

“A “Stitch” in Time: Accurate Timekeeping with On-Chip Compensation→

/ VLSI Conference/

Applications like Energy Meters that rely on real time data require accurate time under all environmental conditions. Typically, these applications rely on Real Time Clock (RTC) for all real time operations but there are many factors like crystal aging, incorrect loading and temperature variations that tend to change the frequency of the clock used for RTC resulting in inaccurate time. Hence there is an unavoidable need to have compensation technique inside the RTC to counter balance this error in clock frequency of crystal. This paper describes a digital hardware compensation technique which compensates by adding or removing pulses in a particular timing window thus maintaining accurate clock. Technique described in this paper uses simple hardware to ensure low power consumption thus maintaining longer battery life. This enables applications to use cheaper crystal that may be inaccurate and compensate for the inaccuracies within the hardware thus reducing board cost.

.entry-summary

Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)

/ Design & Reuse Conference/

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore's Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around 28.7 GHz. Essentially bus-based interconnects are being stretched to the point where they cannot be scaled further. This paper presents challenges with the synchronous (clocked) designs and describes the techniques to overcoming the same with asynchronous (Clockless) design methodology. The paper proposes to redesign the synchronous interconnect to an asynchronous interconnect that should cater to tomorrow's needs of high speed and low power. These circuits work on Handshaking techniques. If not today SOC industry will be forced driven to this methodology tomorrow.

.entry-summary

Secure Your Security Key in on-chip SRAM: Techniques to avoid Data Remanance Attacks→

/ Design & Reuse Conference/

Security protection in modern microcontroller's logic devices with memories is based on the assumption that information from the memory disappears completely after erasing or when the power to the memory is removed. After information in memory is erased there may be some physical characteristics of the memory that allow erased data to be reconstructed. Data Remanence poses a serious threat to widespread applications that support this security protection assumption. This paper presents the effects of Data Remanance and techniques to avoid Security Key retrieval by data remanence attacks.

.entry-summary

Clock Dividers Made Easy→

/ SNUG /

Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. This paper talks about implementation of unusual clock dividers. The paper starts up with simple dividers where the clock is divided by an odd number (Divide by 3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper also covers Verilog code implementation for a non-integer divider

.entry-summary

Read More

Handling Multiple Clocks (Problems & Remedies in Designs involving Multiple Clocks)→

/ SNUG INDIA[2002]/

The scope of this paper deals with issues regarding multiple clock designs and provides short but comprehensive information on the same. Designs involving single clock are like a walk in the park… but the real challenge comes when one has to face more than one clock. Designers are faced with problems of metastability, phase or frequency difference among the clocks involved, performing asynchronous data transfer, etc. This paper covers the issue of multiple clock domains & its problems, by starting with a simple design of a single clock FIFO and later expanding it to dual clock domain and separately detailing on the problems involving more than single clock domains. In short, this paper covers what all a designer needs to make a robust and efficient design involving multiple clock domains.

Read More

Design Tips/tricks for FPGA/ASIC→

/ SNUG INDIA[2002]/

Designing can be anyone’s cup of tea … but it is surely not a bed of roses. Developing a good and robust design is what really matters and contributes to the development of design on FGPA and finally on an ASIC. Tips, tricks and ideas presented in this paper are like a small drop in the ocean of efficient designing techniques, but they surely will help designers to take the first step towards developing efficient designs. The scope of this paper is to provide designers with state machine coding styles, efficient ways of writing code, portability from FPGA to ASIC, implementation of internal memories in FPGA, design tips for multiple clock designs, clock gating, clock management, using resets efficiently, synchronous designs and problem with latches.

.entry-summary

Read More