Today energy theft is a worldwide problem that contributes heavily to revenue losses. Consumers have been found manipulating their electric meters, causing them to stop, under-register or even bypassing the meter, effectively using power without paying for it. This article discusses vulnerabilities, challenges and techniques to prevent tampering in an energy meter.
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Applications like Energy Meters that rely on real time data require accurate time under all environmental conditions. Typically, these applications rely on Real Time Clock (RTC) for all real time operations but there are many factors like crystal aging, incorrect loading and temperature variations that tend to change the frequency of the clock used for RTC resulting in inaccurate time. Hence there is an unavoidable need to have compensation technique inside the RTC to counter balance this error in clock frequency of crystal. This paper describes a digital hardware compensation technique which compensates by adding or removing pulses in a particular timing window thus maintaining accurate clock. Technique described in this paper uses simple hardware to ensure low power consumption thus maintaining longer battery life. This enables applications to use cheaper crystal that may be inaccurate and compensate for the inaccuracies within the hardware thus reducing board cost.
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Embedded electronic control units are finding their way into more and more complex safety critical and mission critical applications. Many of these applications operate in adverse conditions, which can cause code runaway in the embedded control units, putting them into unknown states. A watchdog timer is the best way to bring the system out of an unknown state into a safe state. Given its importance, the watchdog has to be carefully designed, so as to reduce the chances of its operation being compromised by runaway code. This paper outlines the need for robust Watchdog and the guidelines that must be considered while designing a fault tolerant system monitor aka Watchdog. New methods for refreshing a watchdog, write protection mechanism, early detection of code runaway and a quick self-test of the watchdog have been described herein.
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Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore's Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around 28.7 GHz. Essentially bus-based interconnects are being stretched to the point where they cannot be scaled further. This paper presents challenges with the synchronous (clocked) designs and describes the techniques to overcoming the same with asynchronous (Clockless) design methodology. The paper proposes to redesign the synchronous interconnect to an asynchronous interconnect that should cater to tomorrow's needs of high speed and low power. These circuits work on Handshaking techniques. If not today SOC industry will be forced driven to this methodology tomorrow.
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Security protection in modern microcontroller's logic devices with memories is based on the assumption that information from the memory disappears completely after erasing or when the power to the memory is removed. After information in memory is erased there may be some physical characteristics of the memory that allow erased data to be reconstructed. Data Remanence poses a serious threat to widespread applications that support this security protection assumption. This paper presents the effects of Data Remanance and techniques to avoid Security Key retrieval by data remanence attacks.
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Voice over IP offers organizations lower telecommunications costs and greater network efficiency through convergence of voice, data and video. It can be used to stay connected during an emergency or calamity, giving employees access to their phone resources from IP phones at other locations. The rate at which VoIP is growing has given rise to network security concerns that need to be addressed as early as possible. NIST issued a report titled "Security Consideration for Voice Over IP Systems" last year, which focuses on VoIP security problems and recommendations, and highlights the current level of concern.
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Voice over IP offers organizations lower telecommunications costs and greater network efficiency through convergence of voice, data and video. It can be used to stay connected during an emergency or calamity, giving employees access to their phone resources from IP phones at other locations. The rate at which VoIP is growing has given rise to network security concerns that need to be addressed as early as possible. NIST issued a report titled "Security Consideration for Voice Over IP Systems" last year, which focuses on VoIP security problems and recommendations, and highlights the current level of concern.
Voice over IP offers organizations lower telecommunications costs and greater network efficiency through convergence of voice, data and video. It can be used to stay connected during an emergency or calamity, giving employees access to their phone resources from IP phones at other locations. The rate at which VoIP is growing has given rise to network security concerns that need to be addressed as early as possible. NIST issued a report titled "Security Consideration for Voice Over IP Systems" last year, which focuses on VoIP security problems and recommendations, and highlights the current level of concern.
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Using the Globally Asynchronous, Locally Synchronous clock technique, designers can reduce the power consumed by SoCs while simplifying timing requirements.
Adding pipeline stages to a microprocessor core increases performance, but there are a number of potential hazards that need to be overcome in order to achieve a robust and efficient pipelined design.
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Read MoreDividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. This paper talks about implementation of unusual clock dividers. The paper starts up with simple dividers where the clock is divided by an odd number (Divide by 3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper also covers Verilog code implementation for a non-integer divider
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Read MoreThe scope of this paper deals with issues regarding multiple clock designs and provides short but comprehensive information on the same. Designs involving single clock are like a walk in the park… but the real challenge comes when one has to face more than one clock. Designers are faced with problems of metastability, phase or frequency difference among the clocks involved, performing asynchronous data transfer, etc. This paper covers the issue of multiple clock domains & its problems, by starting with a simple design of a single clock FIFO and later expanding it to dual clock domain and separately detailing on the problems involving more than single clock domains. In short, this paper covers what all a designer needs to make a robust and efficient design involving multiple clock domains.
Read MoreDesigning can be anyone’s cup of tea … but it is surely not a bed of roses. Developing a good and robust design is what really matters and contributes to the development of design on FGPA and finally on an ASIC. Tips, tricks and ideas presented in this paper are like a small drop in the ocean of efficient designing techniques, but they surely will help designers to take the first step towards developing efficient designs. The scope of this paper is to provide designers with state machine coding styles, efficient ways of writing code, portability from FPGA to ASIC, implementation of internal memories in FPGA, design tips for multiple clock designs, clock gating, clock management, using resets efficiently, synchronous designs and problem with latches.
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